1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to a method for forming a void-free epitaxial CoSi2 layer which is compatible with ultra-shallow source/drain junctions.
2. Description of Prior Art
Self-aligned silicide (salicide) processes are widely used in semiconductor gate and source/drain structures to reduce sheet resistance. As the gate length of transistors are scaled down for each new generation of integrated circuits (IC) in order to achieve higher speeds and higher density, the source/drain junction depths are also scaled down to reduce the short channel effects. Reduced junction depth can significantly increase the sheet resistance for the source/drain regions. For example, for an 800 angstrom junction depth, a salicide process which consumes 300 angstroms of silicon would reduce the junction thickness by more than a third.
Typically salicide processes use titanium silicide. However, as line widths continue to decrease, titanium silicide becomes impractical. This is because titanium silicide sheet resistance increases dramatically as line widths decrease to about 0.17 microns. Cobalt silicide does not exhibit this line width dependance for sheet resistance, making it an attractive alternative to titanium silicide.
Several method for forming a CoSi2 layer on a shallow source/drain junction have been proposed. In one method, titanium-mediated epitaxy (TIME), a Co/Ti/Si scheme is used. Titanium is deposited onto a silicon structure, preferably by sputtering. Cobalt is deposited onto the titanium, also preferably by sputtering. The substrate is exposed to a two-step anneal in a nitrogen containing ambient, wherein the cobalt and titanium diffuse through one another. The cobalt reacts with the silicon to form CoSi/Co/Si2 and the titanium migrates to the surface and reacts with the nitrogen to form TiN. This process also removes native oxides through a reaction with the titanium to form TiO. The oxygen is released into the chamber ambient when the titanium reacts with the nitrogen.
Another method for forming CoSi2 is oxide-mediated epitaxy (OME), which uses a chemical oxide interfacial layer with multiple deposit-and-ultra-high vacuum (UHV) anneal scheme on an initial CoSi2 layer. However, the UHV in this process increasing fabrication time, reducing throughput. While both methods have demonstrated good epitaxial CoSi2 on flat (blanket) substrates, voids can occur on patterned substrates in high-stress areas such as adjacent to STI structures.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest, and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,047,367 Wei et al. shows a TIME process wherein the epitaxial CoSi2 layer is formed by forming a TiN/CoSi bi-layer, using TiN as a diffusion barrier and as a contact via fill. The titanium layer removes native oxide by reacting with the SiO2 to form titanium oxide (TiOx) which travels to the surface and releases the oxygen to the ambient, and titanium silicide (Ti5Si3 and TiSi2) remains at the silicon interface. However, Wei does not disclose how the TiN diffusion barrier during annealing will survive the subsequent wet etch step. Also, Wei does not disclose or suggest a void formation issue or a method for preventing void formation in his CoSi2 scheme.
U.S. Pat. No. 5,194,405 Sumi et al. shows an OME process for the manufacturing of a semiconductor device using a metal silicide film.
U.S. Pat. No. 5,449,642 Tan et al. shows an OME method of forming a metal_disilicide (MSi2) film.
U.S. Pat. No. 5,728,625 Tung shows an OME process for device fabrication forming an epitaxal CoSi2 layer.
U.S. Pat. No. 5,536,684 Dass et al. shows an OME process designed to form a planar epitaxial CoSi2 layer.
U.S. Pat. No. 5,970,370 Besser et al. shows an unmediated process to form the CoSi2 layer using a Si/Co/TiN/Ti stack and a 2 step RTA. Detrimental contaminations between the silicon and cobalt are prevented by sputter depositing the cobalt layer and the TiN and Ti capping layers in a vacuum.
U.S. Pat. No. 5,567,652 Nishio shows an OME process to form a CoSi2 layer using Si/SiOx/Ti/Co stack and a 2 step RTA.
It is an object of the present invention to provide a method of fabricating a void-free epitaxial CoSi2 layer on a patterned silicon structure.
It is another object of the present invention to provide a method of fabricating a void-free epitaxial CoSi2 layer which is compatible with an ultra-shallow junction.
It is another object of the present invention to provide a method of fabricating an ultra-shallow junction by a diffusion process, using a void-free epitaxial CoSi2 layer as a dopant source.
It is yet another object of the present invention to provide a method of fabricating an ultra-thin (i.e., xe2x89xa6250 angstroms) CoSi2 layer suitable for integration into future sub-0.1 micron CMOS architecture.
To achieve these and other objectives, the present invention provides a method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550xc2x0 C. and 580xc2x0 C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrogen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825xc2x0 C. and 875xc2x0 C. to convert the CoSi layer to a CoSi2 layer. The CoSi2 layer can optionally be implanted with dopant ions which are subsequently diffused to form ultra-shallow junctions.
The present invention provides significant advantages over the prior art. Most significantly, the present invention provides a method for forming a CoSi2 layer which is void free due to reduced stress during annealing, by providing improved control over CoSi/CoSi2 thickness at the silicon interface. Also, the CoSi2 layer formed according to the present invention can be injected with dopant ions and used as a dopant source in a diffusion process to form ultra-shallow junctions with minimal silicon damage.